Design of High Performance Split Path Data Driven Dynamic Full Adders
نویسنده
چکیده
Addition is a fundamental arithmetic operation which is used in different applications such as digital signal processing (DSP) and microprocessors. Single bit adder is the main component of any arithmetic circuit. This paper presents the design of new split-path Data Driven Dynamic (sp-D3L) full adder circuit. Power consumption of proposed adder varies from 0.584 nW to 2.914 nW with variation in supply voltage from 1.8V to 3.3V. Maximum output delay shows variation from 57.18 ps to 423.15 ps with variation of supply voltage from 1.8V to 3.3V. Simulations have been performed using SPICE based on TSMC 0.18μm CMOS technology. Power consumption and delay of proposed adder circuit have been compared with earlier reported circuits and proposed circuit shows significant improvement. Keywords— Arithmetic circuits, CMOS, full adder, PDP, splitpath D3L.
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